ISL6186
2
FN7698.2
November 3, 2011
Simplified Block Diagram
GND
VIN
VIN
EN
FAULT
OUT
OUT
PGD
POR
-V
COMP
+
-
CURRENT AND TEMP.
MONITORING, GATE,
DELAY AND OUTPUT CONTROL
LOGIC
PGD only on 10DFN
Pin Configurations
ISL6186
(8 LD SOIC/DFN)
TOP VIEW
ISL6186
(10 LD DFN)
TOP VIEW
1
2
3
4
8
7
6
5
VIN
OUT
OUT
OUT
FLT
GND
(GND)
EPAD
DFN ONLY
VIN
EN/EN
1
2
3
4
10
9
8
7
VIN
OUT
OUT
PGD
FLT
GND
(GND)
EPAD
5
6
VIN
OUT
VIN
EN/EN
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
8 Ld
SOIC/DFN 10 Ld DFN
1
1
GND IC ground reference
2, 3 2, 3, 4
VIN Chip bias, Controlled Voltage Input, Undervoltage Lock Out (UVLO). V
IN
provides chip bias voltage. At V
IN
< 1.7V, chip functionality is disabled, FLT
is active and floating and OUT is held low. Range 0V to 5.5V
4
5
EN/EN
Enable/Disable inputs, Active high (EN) and active low (EN
) options enable the power switch. These
inputs have internal 1M?pull-off resistors. Range 0V to V
IN